In many applications, analog signals are processed in the analog domain, converted to digital, and then further processed in the digital domain. An analog front-end is a device (in the form of an integrated circuit (IC), separate chip, or stand alone package) that receives an analog signal and performs the analog-to-digital (A/D) conversion. The analog front-end often includes signal conditioning circuits as well.
Because of the continued scaling of CMOS technology, sampling of high speed signals directly at the analog front-end using analog-to-digital converters (ADCs) has been made possible. ADCs convert an analog input signal into a digital output signal by sampling the analog input signal at a sample rate and providing a digital representation of each sample to a specific resolution.
Once the high speed signals are sampled using the ADCs, subsequent signal processing such as equalization and timing recovery can then be accomplished in the digital domain. ADC's for such applications typically require high sample rates (>1 GS/s) at low resolution (4-6 bits), making the flash architecture an attractive choice. A flash ADC uses a linear voltage ladder with a cascaded comparator at each rung of the ladder to compare an input voltage to successive reference voltages, also referred to as thermometer code encoding. For an N-bit flash ADC, the analog front-end has 2N−1 identical comparators in parallel. The comparators are an array of parallel repetitive blocks. Here, the repetitive blocks are formed of comparators and often include pre-amps.
To save power and area while minimizing the ADC's input capacitance, it is highly desirable to use small transistors in the front-end. However, small transistors tend to lead to larger offsets in the comparators, which degrade the linearity of the ADC.
Therefore, effective offset calibration methods are of high interest in order to allow aggressive sizing without sacrificing performance.
ADC calibration can be categorized into foreground calibration and background calibration. A foreground calibration occurs in the signal path and interrupts the ADC operation. Additional device elements, such as switches, are typically arranged in the critical signal path for foreground calibration schemes. High hardware overhead may exist due to captive loads in the critical signal path. In contrast to the foreground calibration, a background calibration is able to track supply and/or temperature fluctuations continuously without interrupting the ADC operation. Some background calibrating techniques include noise injection, random chopping, dynamic comparator array configuration and digital smoothing. In certain background calibration schemes, switching elements are included in the critical signal path, which can degrade ADC performance.
Accordingly, research continues to be conducted to provide improved calibration methods for ADCs.